1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more specifically to a circuit for recognizing an accurate defective condition of a flash memory having an automatic erase function.
2. Description of Related Art
The most typical non-volatile semiconductor memory which is electrically programmable and can be simultaneously erased by one operation (called a "flash memory" hereinafter), includes memory cells each having a floating gate completely covered with an insulator layer. Data is written into this flash memory by injecting charges to the floating gate by means of a hot electron avalanche breakdown or channeling, so that a threshold of a memory cell transistor is raised. On the other hand, an erasing is executed by removing the electric charges from the floating gate by action of a tunneling of the electric charges between the floating gate and a source or a substrate of the memory cell.
In the above mentioned flash memory, because of its memory cell structure suitable to the flash erasing and its erasing manner, some number of memory cells are often disadvantageously over-erased so that a threshold of the memory cells becomes negative, namely, the memory cells are ceaselessly conductive. As a result, all of memory cells connected to a bit line connected to the ceaselessly conductive memory cell seem conductive.
In order to overcome this problem, it has been a conventional practice to write all the memory cells before the flash erasing operation of the memory cells, so that electrons are injected into the floating gate of each memory cell, so as to equalize the charged situation in the floating gate of all the memory cells (pre-erase writing). Thereafter, an erasing operation is actually performed for a time period which is considerably shorter than a time length required to finally completely erase all the memory cells, and then, an erase inspection voltage generated by dropping an external power supply voltage in the inside of the memory device, is applied to a gate of each memory cell, for the purpose of inspecting whether or not all the memory cells are in an erased condition, namely, in a conductive condition. This inspection is called an "erase verify" hereinafter.
The operation consisting of the erase and the erase verify is succeedingly repeated many times until data has been completely erased from all the memory cells. Thus, in the prior art, it has been attempted to equalize the erased situation of each memory cell (namely, to minimize a variation of the erased condition, thereby to equalize the threshold of each erased memory cell).
Furthermore, with increase of a memory capacity, possibility that a memory array mixedly includes memory cells having erasing speeds greatly different from one another, elevates. Therefore, it has been also attempted to divide the memory, cell array into a plurality of memory cell blocks and to perform the above mentioned memory erasing operation for each one memory cell block, so that the whole of the memory cell array is equally erased (See Japanese Patent Application Laid-open Publication No. JP-A-05-182479, which corresponds to U.S. Pat. No. 5,327,384, the disclosure of which is incorporated by reference in its entirety into this application).
Referring to FIG. 1, there is shown a block diagram illustrating one example of a conventional flash memory, which is conceptionally similar to the disclosure of JP-A-05-182479 and U.S. Pat. No. 5,327,384. As shown in FIG. 1, the conventional flash memory includes a data input/output circuit 1 coupled to a data input/output terminal I/O, a write circuit 2, a read circuit 3, a column selector 4, a column decoder 5, a row decoder 6, a memory cell array 7 divided into a plurality of blocks, an erase circuit 8 including block erase circuits No. 1 and No. 2 provided for controlling the erase for each one memory cell block, an erase discrimination circuit 9, a control circuit 11, an internal address generator 12, and an address input circuit 13 coupled to a group of address signal input terminals A0 to Ai, which are coupled as shown.
In addition, Reference Numerals S21 and S31 designate various internal signals. If data to be written is supplied through the data input/output terminal I/O to the data input/output circuit 1, an internal data signal S21 is supplied from the data input/output circuit 1 to the write circuit 2, from which an internal data signal S22 is supplied to the column selector 4, so that the data signal is written into the memory cell array 7. On the other hand, an internal data signal S23 read out from the memory cell array 7 is supplied through the column selector 4 to the read circuit 3, from which an amplified internal read-out data signal S24 is supplied to the data input/output circuit 1, so that the read-out data is outputted from the data input/output circuit 1 to the data input/output terminal I/O.
The amplified internal read-out data signal S24 is also supplied to the erase discrimination circuit 9, which generates an erase discrimination signal S25 to the control circuit 11, which in turn generates a control signal S26 to the internal address generator 12 and the address input circuit 13. The control circuit 11 also generates an erase control signal S27, which are supplied to the column decoder 5, the row decoder 6 and the erase circuit 8. The block erase circuits No. 1 and No. 2 of the erase circuit 8 supply erase voltage signals S29 and S28 to the corresponding memory cell blocks of the memory cell array 7, respectively. An address S30 is supplied through the address input terminals A0 to Ai to the address input circuit 13, which generates an internal address S32. This internal address S32 and another internal address S31 generated by the internal address generator 12, are supplied to the column decoder 5, the row decoder 6 and the erase circuit 8.
As mentioned above, in the conventional flash memory, the larger the number of memory cells becomes, the large the degree of variation in the erasing speed between a memory cell having the highest erasing speed and a memory cell having the lowest erasing speed becomes. As a result, when it is confirmed by the erase verify that the memory cell having the lowest erasing speed has been erased, the memory cell having the highest erasing speed becomes a ceaselessly conductive condition, namely, an over-erased condition. Namely, an erase defective occurs, and therefore, a stable erasing operation becomes difficult.
In addition, if the memory array is divided into a plurality of blocks and an erasing operation is controlled for each one block, probability of the erase defective drops, however, the possibility of the erase defective never becomes zero, because this is not an essentially solving means.
Furthermore, in the conventional erasing manner for the flash memory, since the erasing operation is repeated until the memory cell having the lowest erasing speed has been erased, if a memory cell which cannot be erased completely is included in the memory cell array, the memory device is put into the over-erased condition, namely, becomes defective. This means that an accurate repairing decision cannot be made in a wafer checking step based on the precondition that the memory device is repaired by use of a redundancy. Namely, a memory device having only a few bits of memory cells which cannot be erased, namely, a memory device which can be repaired by use of the redundancy, is put into the over-erased condition of the whole of the memory cell array, which can no longer repaired by use of the redundancy. As a result, the yield of production drops.
In a procedure for accurately repairing the memory device including memory cells which cannot be completely erased, by use of the conventional circuit, the "erasing" and the "erase verify" are repeated on the basis of an algorithm of the checking system, not by an automatic control basis. However, this procedure requires a voluminous time for the data processing in the checking, system, and a long offset time for the device measurement. Accordingly, the wafer checking processing drops a mass production efficiency.